A prior art D-type flip-flop circuit formed by first and second latch circuits is illustrated in FIG. 1. The first latch is provided by an MOS first passgate PSGT1 having a first input V.sub.IN for receiving data signals, a first output n1 for transmitting data signals in the transparent operating mode, and an MOS first latchback circuit LTBK1 for latching a data signal at the non-inverting first output node n1. An inverting output of LTBK1 is provided at node n2. The second latch is provided by an MOS second passgate circuit PSGT2 having a second input coupled to the inverting output n2 from first latchback circuit LTBK1 and a second and final output (V.sub.OUT) which charges and discharges load capacitance C.sub.L coupled to the final output. An MOS second latchback circuit LTBK2 is coupled to the second output V.sub.OUT for latching a data signal at the final output.
When clock signal CP is at high potential level, clock signal CP is at low potential level. Passgate NMOS transistor element QN1 and PMOS transistor element QP1 are both conducting and the first passgate PSGT1 is in the transparent operating mode. A data signal applied at the first input V.sub.IN therefore appears at the first output n1 and is latched by latchback circuit LTBK1 provided by CMOS inverter stages INV2,INV1. An inverted data signal is latched by the first latchback circuit LTBK1 at node n2 which provides the input-to second passgate PSGT2.
With clock signals CP high and CP low the passgate NMOS transistor element QN2 and PMOS transistor element QP2 are not conducting and the second passgate circuit PSGT2 is in the blocking mode. When the clock signals switch to CP low and CP high the second passgate circuit PSGT2 becomes transparent passing the inverted data signal from node n2 to the second output V.sub.OUT where it is latched by the second latchback circuit LTBK2. The MOS inverter stages INV3,INV4 of LTBK2 are coupled to provide a non-inverting latch of data signals at V.sub.OUT. The final output data signal at V.sub.OUT is therefore inverted with respect to the corresponding input data signal at the first input V.sub.IN.
The clock signals CP and CP are derived from original clock signal CLK by the clock buffer illustrated in FIG. 2. The speed of the flip-flop or latchable buffer circuit is the standard signal propagation delay time measured from the occurrence of the original clock signal CLK to occurrence of the output high or low potential level data signal at the final output V.sub.OUT. A disadvantage of the flip-flop circuit of FIG. 1 is that the signal propagation delay time T.sub.P CLK/V.sub.OUT according to the standard measure is dependent upon and delayed by an RC time constant. The capacitance of the RC time constant is the capacitance associated with the CMOS inverter gate INV4 of the output latchback circuit LTBK2 and the load capacitance C.sub.L. The load capacitance C.sub.L is for example associated with the next stage coupled to the final output V.sub.OUT. The resistance in the RC time constant is inversely proportional to the size and therefore current carrying capacity of the second passgate transistor elements QN2, QP2 and the drive transistor elements of CMOS inverter gate INV2.
If the layout area in the IC geometry is not an issue, the size of the passgate transistor elements QN2, QP2 of passgate PSGT2 as well as the size of the pullup and pulldown transistor elements of CMOS inverter gate INV2 may be increased until a desired propagation delay T.sub.P CLK/V.sub.OUT is achieved. However as the size of the passgate transistor elements increases, the capacitive log charged and discharged by clock pulse signals CP and CP also increases. Eventually the operating time of the clock buffer of FIG. 2 will slow down because of the time required for charging and discharging the gate electrodes of the passgate transistor elements. Furthermore additional IC layout space is required for the geometry of the larger transistors.